Welcome Address
B.M. Al-Hashimi (Univ. of Southampton, UK) - ETS'06 General Chair

Keynote: Innovation and Wealth Creation from Technology
R. Saxby (ARM, UK)

Presentation of ETS'05 Best Paper Award
M. Renovell (LIRMM, FR) - ETS'05 Program Chair

Invited Address: Living with Failure: Lessons From Nature?
S. Furber (Univ. of Manchester, UK)

Introduction to ETS'06 Technical Program
E.J. Marinissen (Philips Research, NL) - ETS'06 Program Chair

Practical Aspects of ETS'06
M. Zwolinski (Univ. of Southampton, UK) - ETS'06 Local Arrangements Chair

Input Cones Based on Test Sequences for Synchronous Sequential Circuits
I. Pomeranz (Purdue Univ., US), S. Reddy (Univ. of Iowa, US)

Strengthening Logic BIST with IDDQ - Taking the Best of Both Worlds
J.S. Vaccaro, T. Colunga, L. Benecke, S. Mahadevan (Freescale Semiconductor, US), H. Manhaeve (Q-Star Test, BE)

Extended Compatibilities for Scan Tree Construction
Z. You, M. Inoue, H. Fujiwara (Nara Inst. of Science and Tech., JP)

Proposal of a Clock Signal Generation/Detection Method for Crosstalk Aware Design
Y. Miura (Tokyo Metropolitan Univ., JP)

Efficient and Accurate Analog Sinewave Generator for BIST Applications
M.J. Barragán, D. Vazquez, A. Rueda, G. Huertas, J.L. Huertas Diaz (Univ. de Sevilla, ES)

Some Improvements of Phase-Spectrum ADC Hysteresis Test for Practical Application
D. Slepicka, D. Dallet (Laboratoire IXL, FR), V. Shitikov, F. Barbara (Schlumberger, FR)

Bitline-Coupled Precharge Faults and Their Detection in Memory Devices
Z. Al-Ars, S. Hamdioui (Delft Univ. of Tech., NL), G. Müller, J. Vollrath (Infineon Technologies, DE)

Automatic Test Program Generation Tool for Mixed-Signal Device Interface Boards
B. Kim (Univ. of Alabama, US), V. Kalyanaraman, P. Variyam (Texas Instruments, US), S. Cherubal (WiQuest Communications, US)

Low Cost Launch-on-Shift Delay Test with Slow Scan Enable Signals
G. Xu, A. Singh (Auburn Univ., US)

Dynamic Voltage Scaling Aware Delay Fault Testing
N.B. Zain Ali, M. Zwolinski, B.M. Al-Hashimi (Univ. of Southampton, UK), P. Harrod (ARM, UK)

Enhancing Delay Fault Coverage through Low Power Segmented Scan
S. Reddy, Z. Zhang (Univ. of Iowa, US), J. Rajski (Mentor Graphics, US), B.M. Al-Hashimi (Univ. of Southampton, UK)

Single-Event Upset Analysis and Protection in High Speed Circuits
M. Hosseinabady, P. Lotfi-Kamran (Univ. of Tehran, IR), G. Di Natale, S. Di Carlo, A. Benso, P. Prinetto (Politecnico di Torino, IT)

Soft Error Resilient Linear DSM Systems: Probabilistic Error Correction vs. State Restoration
M. Ashouei, S. Bhattacharya, A. Chatterjee (Georgia Inst. of Tech., US)

Avoiding Circuit Simulation for the Analysis of Single Event Transient Propagation in Combinational Circuits
C. Neves (Univ. Federal de Pelotas, BR), I. Ribeiro, E. Henes, G. Wirth (UERGS, BR), F. Lima Kastensmidt (UFRGS, BR), J.L. Güntzel (UFPEL, BR)

Test Management Systems - A New Category in the Testing Arena
D. Glotter (OptimalTest, Israel)

The Growing Impact of Manufacturing Test - Enabling DPM Reduction and Yield Learning
J. Rajski, B. Watt (Mentor Graphics, US)

Visibility Enhancement for Silicon Debug
Y.-C. Hsu, R. Ruiz (Novas Software, US)

Minimal March Tests for Dynamic Faults in Random Access Memories
G. Harutunyan, V. Vardanian (Virage Logic, Armenia), Y. Zorian (Virage Logic, US)

A 22n March Test for Realistic Static Linked Faults in SRAMs
A. Benso, A. Bosio, S. Di Carlo, G. Di Natale, P. Prinetto (Politecnico di Torino, IT)

Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories
Y.-J. Huang, J.-F. Li (National Central Univ., TW)

Fault Identification in Reconfigurable Carry Lookahead Adder Implementations Targeting Nanoelectronic Fabrics
W. Rao, A. Orailoglu (UCSD, US), R. Karri (Polytechnic Univ., US)

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices
K. Katoh, H. Ito (Chiba Univ., JP)

Fault Injection-based Reliability Evaluation of SoPCs
M. Sonza Reorda, L. Sterpone, M. Violante (Politecnico di Torino, IT), M. Portela-Garcia, C. Lopez-Ongil, L. Entrena (Univ. Carlos III de Madrid, ES)

Consideration of On-Chip Compression Alternatives
R. Illman (Cadence Design Systems, UK), B. Keller (Cadence Design Systems, US)

Keeping Test Simple
R. Kapur (Synopsys, US)

Facilitating At-Speed Test at the Register Transfer Level
S. Swaminathan (Qualcomm, US), R. Marlett (Atrenta, US)

Modeling and Automatic Test Pattern Generation for Mixed-Signal Boards in Maintenance Testing: Dealing With Simple Time Aspects
B. Gilles (Univ. de Bretagne Occidentale, FR)

Accurate IDD Testing of Mixed-Signal Integrated Circuits using Auto-Zero Voltage Comparator
V. Nagy, V. Stopjaková (Slovak Univ. of Tech., Slovakia)

Hardware Implementation of the Backtrace Algorithm
M. Stáva, O. Novák (Czech Tech. Univ., CZ)

Small Delay Defect Detection in the Presence of Process Variations
R. Tayade, S. Sundareswaran, J. Abraham (Univ. of Texas-Austin, US)

Connectionless Testing
M. Salamati, D. Stranneby (Orebro Univ., SE)

STESOC: A Software-Based Test Access Mechanism
M. Tuna, M. Benabdenbi, A. Greiner (Univ. of Paris VI, FR)

An Efficient Online BIST Architecture for NoCs
M. Hosseinabady, M. Nazm Bojnordi, A. Banaiyan, Z. Navabi (Univ. of Tehran, IR)

Retention-Aware Test Scheduling for BISTed Embedded SRAMs
Qiang Xu (Chinese Univ. of Hong Kong, HK), B. Wang (ATI Technologies, CAN), F.Y. Young (Chinese Univ. of Hong Kong, HK)

A Transparent-Based Programmable Memory BIST
S. Boutobza (Synopsys, FR), M. Nicolaidis (TIMA Laboratory, FR)

A Flexible and Scalable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare
B. Laquai, M. Hua, G. Schulze, M. Braun (Agilent Technologies, DE)

On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
M. Collins, B.M. Al-Hashimi (Univ. of Southampton, UK)

Moving Jitter Injection for High-Speed Digital Streams from the Analog Domain to the Digital Domain
R. Whyte (Credence, UK)

High Throughput PLL Testing - A Fast Method to Test Frequency and Jitter on Clock Outputs in Production
M. Braun, M. Fischer, J. Wolf (Agilent Technologies, DE)

Screening is rejecting chips that pass all tests, but are suspect of being test escapes or latent reliability problems. Screening can for example be done on wafer neighborhoods (a die with too many failing dies as neighbors is suspect) or on parametric outlier measurements (a die with measurement values within spec, but sufficiently different from other passing dies). This panel session will discuss screening and its implications. What hardware and software
infrastructure is necessary to enable screening? How effective is screening, and how is that measured? How expensive is screening; aren't we simply throwing away good dies? How does screening relate to burn-in? And, shouldn't we be improving our tests themselves?

Panelists:

* Tom S. Barnett (IBM Microelectronics, US)
* Dan Glotter (OptimalTest, Israel)
* Bob Madge (LSI Logic, US)
* Adit Singh (Auburn University, US)
* Co van Winsum (Philips Semiconductors, NL)

Universities strive to define appealing curricula to attract and educate top students and perform research that will impact long term industry needs. Employers look for skillful employees who can tackle the problems that require immediate solutions and who also have the depth to foresee the challenges of tomorrow. Given both the common interests and cultural differences between academia and industry, the question is how can we further improve the academic preparation to better serve the (test) industry in the long run? Join recent university graduates who will share their experience in transitioning from student to profession.

Panelists:

* Zaid Al-Ars (Delft Univ. of Tech., NL)
* Thomas Clouqueur (AMD, US - ex Univ. of Wisconsin-Madison, US)
* Artur Jutman (Tallinn Univ. of Tech, EST)
* Martin Keim (Mentor Graphics, US - ex Univ. of Freiburg, DE)
* Krishna Chakravadhanula (Cadence, US - ex Univ. of Texas-Austin, US)
* Ross Torkington (ARM, UK - ex Sheffield Univ., UK)
* Erik Volkerink (Agilent Technologies, US - ex Stanford Univ., US)

The EDA vendors have risen to the challenges of improved test-synthesis tools for at-speed test, test-data compression, and repairable memories. The ATE vendors have improved the capabilities of semiconductor testers in terms of measurements on high-speed buses: jitter injection and analysis, bit-error rate assessment, etc. So, what's next? What will be the major challenges of the test-synthesis and test-application vendors over the next five years as we drive down into 65nm technologies? More of the same, or something radically different? Come listen to the experts foretelling the future.

Panelists:

* Rob Aitken (ARM, US)
* Rohit Kapur (Synopsys, US)
* Janusz Rajski (Mentor Graphics, US)
* Jochen Rivoir (Agilent Technologies, DE)
* Robert Ruiz (Novas, US)
* Mike Tegethoff (Cadence, US)

On-Chip Test Generation Using Linear Subspaces
R. Das, I.L. Markov, J.P. Hayes (Univ. of Michigan, US)

Convolutional Compactors with Variable Polynomials
A. Pogiel (Poznan Univ., PL), J. Rajski (Mentor Graphics, US), J. Tyszer (Poznan Univ., PL)

Deterministic Logic BIST for Transition Fault Testing
V. Gherman, H.-J. Wunderlich (Univ. Stuttgart, DE), J. Schlöffel, M. Garbers (Philips Semiconductors, DE)

Experimental Validation of a Fully Digital BIST for Cascaded SD Modulators
G. Leger, A. Rueda (Inst. de Microelectrónica de Sevilla, ES)

Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits
E. Schüler, D. Scain Farenzena, L. Carro (UFRGS, BR)

Bit-stream Manipulation for SD Modulator Failure Mode Detection
K. Georgopoulos, A. Lechner, A. Richardson, M. Burbidge (Lancaster Univ., UK)

Design for Yield with Embedded Tester for Memory Subsystem in SoC
R. Chandramouli (Virage Logic, US)

Demystifying Repairable Memory
R. Aitken (ARM, US)

IDD(Q) Application to Analog and Mixed-Mode Circuits - A Case Study
S. Jing, A. Mathie, J. Garrison (National Semiconductor, US), H. Manhaeve (Q-Star Test, BE)

Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Resistive Bridging Fault Model and n-Detect Test
S. Biswas, A. Patra, S. Mukhopadhyay, D. Sarkar (IIT Kharagpur, IN)

Outliers Screening with Multiple Parameter Correlation Testing for Analogue ICs
L. Fang, M. Lemnawar, Y. Xing (Philips Semiconductors, NL)

Failure Mechanisms due to Process Variations in Nanoscale SRAM Core-Cells
P. Girard, S. Pravossoudovitch, A. Virazel (LIRMM, FR), M. Bastian (Infineon Technologies, FR)

An Information-Redundant Scheme for On-Line Testing of an Asynchronous ALU Operation
M.J. Marshall, G. Russell (Univ. of Newcastle-upon-Tyne, UK)

An Approach to Reduce Over-testing of Path Delay Faults in Data Paths Using RTL Information
Y. Yoshikawa, S. Ohtake, H. Fujiwara (Nara Inst. of Science and Tech., JP)

Detecting Hard-Faults Masked by Manufacturing Process Variations: a DAC Example
C. Wegener, M.P. Kennedy (Univ. College Cork, IRL)

On the Use of Multi-Clock, Multi-VDD and Multi-Temperature Schemes to Improve Dynamic Fault Detection in Digital Systems
Marcial Rodriguez-Irago, J.J. Rodriguez Andina (Univ. of Vigo, ES), F. Vargas (PUCRS, BR), J. Semião (Univ. Algarve, PT), I. Teixeira, J.P. Teixeira (IST/INESC-ID, PT)

A Parallel Multilevel-Huffman Decompression Scheme for IP Cores with Multiple Scan Chains
X. Kavousianos (Univ. of Ioannina, GR), E. Kalligeros, D. Nikolos (Univ. of Patras, GR)

Effects of Multiple Non-Concurrent Faults on Microprocessor Operation
E. Touloupis, J.A. Flint, V.A. Chouliaras (Loughborough Univ., UK), D.D. Ward (MIRA, UK)

Testing and Diagnosis of Power Switches in SOCs
S.K. Goel, M. Meijer, J. Pineda de Gyvez (Philips Research, NL)

A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications
M. Cimino, H. Lapuyade, M. De Matos, T. Taris, Y. Deval, J.B. Bégueret (IXL Laboratory, FR)

Detecting Subtle IDDQ Faults by Using an Optimized Model-Based Estimator
J. Schat (Philips Semiconductors, DE)

 "Analogue Network of Converters": A DFT Technique to Test a Complete set of ADCs and DACs Embedded in a Complex SiP or SOC
V. Kerzérho (LIRMM, FR), P. Cauvet (Philips Semiconductors, FR), S. Bernard, F. Azaïs, M. Comte, M. Renovell (LIRMM, FR)

Reducing Sampling Clock Jitter to Improve SNR Performance of A/D Converters in Production Test
S. Goyal, A. Chatterjee (Georgia Inst. of Tech., US), M. Atia (National Semiconductor, US)

Design-Based Structural Test Method for Stereo DAC
L. Ma, G. Seuren, R. van Rijsinge, C. Bastiaansen, L. van der Dussen (Philips Semiconductors, NL)

Improving Automotive IC Quality - A Case Study on the Implementation of Advanced IDDQ Strategies Targeting Product Quality Improvement, Burn-In Elimination and Test Cost Reduction
M. Schmid, R. Flassak, A. Patitz (Dialog Semiconductor, DE), H. Manhaeve (Q-Star Test, BE)

High-Efficiency Multi-Site Test for SiP Mobile Technologies
J. McEleney (Teradyne, US)

Involving Academia in Leading Edge Semiconductor Test Technology
P. Roddy (Advantest America, US)

Fault Collapsing for Transition Faults Using Extended Transition Faults
I. Pomeranz (Purdue Univ., US), S. Reddy (Univ. of Iowa, US)

FATE: a Functional ATPG to Traverse Unstabilized EFSMs
G. Di Guglielmo, F. Fummi, C. Marconcini, G. Pravadelli (Univ. di Verona, IT)

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults
N.B. Devta-Prasanna (Univ. of Iowa, US), A. Gunda, P. Krishnamurthy (LSI Logic, US), S. Reddy (Univ. of Iowa, US)

Session 12B: Advanced Analog Testing
Moderators: L. Carro (UFRGS, BR) and M. Renovell (LIRMM, FR)

 A Low-Cost Alternative Method for Harmonics Estimation in a BIST Context
V. Fresnaud, L. Bossuet, D. Dallet (Univ. of Bordeaux, FR), S. Bernard (LIRMM, FR), J.M. Janik (Univ. of Caen, FR), B. Agnus, P. Cauvet, Ph. Gandy (Philips Semiconductors, FR)

Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters
B. Kim, H. Shin (Univ. of Texas-Austin, US), J.H. Chun (Intel, US), J. Abraham (Univ. of Texas-Austin, US)

Low-Cost Parametric Failure Diagnosis of RF Transceivers
D. Han, S. Bhattacharya, S. Goyal, A. Chatterjee (Georgia Inst. of Tech., US)

The Analysis of the Implementation of Concurrent Error Detection in Multi-Level Flash Memories
B. Halak, G. Russell (Univ. of Newcastle-upon-Tyne, UK)

On-Chip Micro Programmable BIST for High SRAM Test Coverage
R. Zappa, C. Selva, D. Rimondi, C. Torelli (STMicroelectronics, IT)

Diagnosis in Designs with Block Compactors
T. Clouqueur (Nara Inst. of Science and Tech., JP), K. Zarrineh (AMD, US), K.K. Saluja (Univ. of Wisconsin-Madison, US), H. Fujiwara (Nara Inst. of Science and Tech., JP)

Estimation of RF IC Specifications Based on DC Tests
S. Ellouz, P. Gamand, C. Kelma (Philips Semiconductors, FR), B. Vandewiele (Philips Research, NL), B. Allard (Cegely Insa-Lyon, FR)

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing
N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel (LIRMM, FR), H.-J. Wunderlich (Univ. Stuttgart, DE)

A CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization
A. Bounceur, S. Mir (TIMA Laboratory, FR), L. Rolíndez (ST Microelectronics, FR), E. Simeu (TIMA Laboratory, FR)

Investigation of Single-Cell Dynamic Faults in Deep-Submicron Memory Technologies
S. Hamdioui, Z. Al-Ars, G. Gaydadjiev (Delft Univ. of Tech., NL), J.D. Reyes (Intel, US)

Fault Tolerance Against SEUs using Memory-Based Circuits to Improve the Architecture Vulnerability Factor
E. Rhod, C. Lisbôa, A. Michels, L. Carro (UFRGS, BR)

Stuck-At Fault Testing of FPGA Cores using Standard Test Pattern Generation Tools
M. Bennebroek, H. Vranken, A. Danilin (Philips Research, NL)

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
A. Amory (UFRGS, BR), K. Goossens, E.J. Marinissen (Philips Research, NL), M. Lubaszewski (UFRGS, BR), F. Moraes (PUCRS, BR)

A DFT Architecture for Asynchronous Networks-on-Chip
X.-T. Tran, J. Durupt, F. Bertrand (CEA-LETI, FR), C. Robach, V. Beroulle (INPG/ESISAR, FR)

Low-Cost Online Testing of Asynchronous Handshakes
D. Shang, A. Yakovlev, F. Burns, F. Xia, A. Bystrov (Univ. of Newcastle-upon-Tyne, UK)

Test-per-Clock Detection, Localization and Identification of Interconnect Faults
M. Kopec, T. Garbolino, K. Gucwa, A. Hlawiczka (Silesian Univ. of Tech., PL)

On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture
F. Pöhl (Infineon Technologies, DE), J. Rzeha (Univ. of Potsdam, DE), M. Beck (Infineon Technologies, DE), M. Gössel (Univ. of Potsdam, DE), R. Arnold, P. Ossimitz (Infineon Technologies, DE)

CMOS Defects Analysis using DefSim Measurement Environment
W.A. Pleskacz, T. Borejko, A. Walkanis (Warsaw Univ. of Tech., PL), V. Stopjakova (Slovak Univ. of Tech., Slovakia), A. Jutman, R. Ubar (Tallinn Univ. of Tech., EST)

Implementing the Gate Delay Test Method on a DECT Base-Band Design
J. ten Pierick (Philips Semiconductors, CH)

SiP Testing - An Industrial Case Study
H. Eichinger, G. Scheer (Infineon Technologies, AU)

An Industrial Approach to Re-order Integrated Circuit Tests to Maximize Test Benefit
S. Krishan, A. Zjajo (Philips Research, NL)